Publications 2010

Embedded Systems used for control, for example in Cyber-Physical-Systems (CPS), perform the monitoring and control of complex physical processes using applications running on dedicated execution platforms in a resource-constrained manner. Application-specific System-On-Chip (SoC) designs providing the execution platform have advantages compared with traditionally used program-controlled multiprocessor architectures. SoC designs can be modelled on structural and behavioural level. The behavioural level is generally a more sophisticated modelling level. In the context of CPS, these are mainly reactive systems with dominant and complex control paths. The major contribution to concurrency appears on control path level. A new SoC design methodology is presented using the behavioural hardware compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes (CSP) with an extensive set of interprocess- communication primitives and guarded atomic actions. The programming language and the compiler-based synthesis process enables the design of constrained power- and resource-aware embedded systems with pure Register- Transfer-Logic efficiently mapped to FPGA and ASIC technologies. Concurrency is modelled explicitly on control- and datapath level. Additionally, concurrency on datapath level can be explored and optimized automatically by different schedulers. The CSP programming model can be synthesized to different levels, not only used for hardware circuit synthesis: software models (C, ML), intermediate μCode, RTL state level, and finally VHDL. A common source for both hardware and software implementation with identical functional behaviour is used.

As the numbers of available high performance but low-power embedded system rise, new application scenarios for tailored sensor systems get in reach to be implemented. In some cases battery powered or selfpowered systems are needed, e.g. in the context of wireless sensor networks. The question has to be considered, if the system has enough energy and always enough power to fulfil its task. Often the answer can only be given, in case the analysis is carried out in the context of the real application. A simulation on this will only be meaningful, if it describes the environmental condition of this context as well. Therefore we propose a simulation toolbox for energy and power analysis of independent sensor nodes. This presentation shows the foundations of a new simulation toolbox, a tool for designing modular sensor systems. The focus of this tool will be on the economic and efficient use of power and energy on the level of embedded systems. The base of the toolbox is a growing number of simulation blocks modelling the power behaviour of embedded modules like energy sources, converters, storage and load. A set of tools for observing losses, energy throughput and power lags, assists the system designer to set up an economic solution. A strong emphasis lies on the modelling of modern energy harvesting principles and the embedding physical situation. One main goal of this research work is to overcome the principle of always oversizing the power supply of electric system for the worst case. Instead a situation-dependant adaptive energy management will set different operation modes of embedded systems to cope with power supply and energy situation. Therefore these systems will act much more reliable than the traditional ones. To save energy, the different operation modes will lead to a tailored sensor data processing. Instead of using a full micro processor, the next development steps are configurable hardware blocks. Therefore the load models will consider different implementations on work task level. A simple but comprehensible example will show the possibilities of system analysis and should lead to a productive discussion about future enhancements from the point of view of system designers and users.

Communication gains impact with increasing miniaturization and densities in sensor- and actuator networks, especially in the context of robotics and sensorial materials - they require basically wired networks. The sensor network is a massive parallel computer performing data fusion with smart nodes, requiring a functional system design flow. Traditionally, there are two different ways to model and implement System-on-Chip designs (SoC) used in highly miniaturized sensor- and actuator networks: using a structural and/or · using a behavioural model level. Parallelism is mostly required to satisfy system latency time, resource, and power constraints.

Copying nature, engineering science aims at providing technical structures with an analogue of a nervous system in terms of networks of sensors, communication facilities linking these and specific hardware as well as computational methods to derive meaning from their combined signals. For the latter task, artificial intelligence approaches constantly gain importance; the more so as the trend of ever increasing sensor network size and density suggests that sensor and structure may soon become one, forming a sensorial material. Current simulation techniques capture many aspects of sensor networks and structures. For decision making and communication, multi agent based simulation (MABS) is an accepted method, as is finite element analysis (FEA) for structural behaviour. To take advantage of developments in sensorisation and gain knowledge of what sensorial materials mean, a monitoring system was designed which is able to deduce the loads applied as well as violations of design rules from sensor information and structural subsystem response. The concept behind this is that instead of having been designed to loads and tested to conditions, the structural model, and, in its physical realisation, the material or structure, can experience and report design constraint violations. We present first results of the modelling and simulation approach obtained in experiments done with a strain gauge equipped plate using optical surface metrology to gain reference values of local strain.

Communication gains impact with increasing minaturization and densities in sensorand actuator networks, especially in the context of robotics and sensorial materials. System-On-Chip design on Register-Transfer-Logic (RTL) level using FPGA and ASIC technologies enables 1. small sized integration of sensors and data processing units (DPU) scaled down to one-chip designs using ASIC- and MEMS technology, and 2. satisfies low power requirements, required especially for high density sensor networks sourced by environmental energy (energy harvesting). But using resource and power aware designs constraint algorithm complexity significantly, concerning control, data processing, and communication. Software based communication approaches, like TCP/IP based, can not be implemented entirely in hardware, and they are still too complex. Another important quality of communication in sensor- and actuator networks is reliability and robustness against link failures Thus, communication protocols aligned to low resource and low power designs are required. Most actual work in communication focus on wireless networks [4]. But sensorial materials and highly integrated robotics systems require basically wired networks. The network topology of sensor- and actuator networks is in generally distributed and decentralised, and nodes of such a network have different computing power and storage, resulting in the following constraints for protocol design: 1. message based point-to-point communication, 2. application specific scalable protocol regarding network and data sizes to satisfy A. low power design, and B. reducing computing and storage requirements, 3. no unique node addressing (not usable in high density sensor networks), 4. simple routing strategies, but finally 5. robustness related to alternative path finding.

Traditionally, there are two different ways to model and implement System-On-Chip-Designs (SoC): using a structural and/or a behavioural level. The structural level decomposes a SoC into independent submodules interacting with each other using centralized or distributed networks and communication protocols. The behavioural level usually describes the behaviour of the full design interacting with the environment. Complex reactive systems with dominant and complex control paths play an increasing role in SoC-design. The major contribution to concurrency appears on control path level. This article gives an introduction to SoC-design methodology using the behavioural hardware compiler ConPro providing a programming model based on concurrent communication sequential processes (CSP) with an extensive set of interprocess-communication primitives. An extended case study of a communication protocol used in high density sensor-actuator-networks should demonstrate the design of a SoC for a robot actuator. The communication protocol is suited for high-density intra- and interchip networks.